In this specification, the term “MOS” is used in its generally-accepted sense, which is not restricted either to metal (for gate electrodes) or to oxide (for gate dielectrics). A “device” generally refers to a transistor, although it will be understood that transistors are capable of use in many different ways, including as switches in digital circuits and amplifying elements in analog circuits.
Scaling of MOS devices faces considerable challenges as the device dimensions become as small as a few atoms in thickness. In particular, short-channel effects and leakage current become increasing problems. The channel (or channel region) of a MOS transistor (MOSFET) is a conduction zone within a body of the transistor, extending between a source and a drain. Short-channel effects such as drain-induced barrier lowering (DIBL) result from the high electric field strengths resulting within the device as the device dimensions, and thus the channel length, shrink. Leakage current tends to increase exponentially as channel length, and/or the thickness of a gate dielectric (see below) is reduced, making the transistor impossible to turn off completely. Such leakage current may account for a large proportion of the power consumed by an integrated circuit (IC) made up of such devices. Reducing the operating voltage, which is a requirement according to the ITRS (International Technology Roadmap for Semiconductors) only partly mitigates these effects.
Conventionally, MOS devices are planar bulk devices. “Planar” means that the structure is essentially in-plane with the surface of the substrate, and “bulk” means that the body, source and drain are formed within a thick silicon substrate. The source and drain may be made by doping the substrate to form regions of n-type semiconductor material—giving a nMOS; or by forming regions of p-type material giving a pMOS. The body, generally also doped, is of opposite conductivity type to the source and drain. For an nMOS device a p-type channel region may be present, whereas for a pMOS device a n-type channel region may be present. Frequently, nMOS and pMOS devices are combined in the same semiconductor device in a technology called CMOS (Complementary Metal Oxide Semiconductor), to exploit the properties of both types of transistor.
Normally a single gate is formed on top of the body to control the transistor. More precisely, a “gate stack” is constructed comprising a gate electrode of metal or semiconductor material or a combination thereof, on top of gate oxide comprising one or more dielectric layers.
Control of the channel via the gate is of great importance to reduce short-channel effects and leakage current. One approach to enhancing the control afforded by the gate is to reduce the thickness of the dielectric layer (gate oxide); however, this tends to increase the leakage current owing to quantum-mechanical tunneling between the gate electrode and the channel. More stringent gate oxide requirements follow from this, such as the need for materials with a higher dielectric constant.
Another measure is to replace the thick silicon substrate by a relatively thin silicon layer on a substrate of insulating material, so-called silicon-on-insulator (SOI). The insulating material is normally a buried oxide layer, referred to as BOX. A typical standard thickness of the BOX is 145 nm. In this way the gate is able to exert control throughout the volume of the body rather than only in a surface region.
Unlike in bulk devices, the body may be partially depleted of charges (PDSOI)—or, if the body is very thin, fully depleted (FDSOI). In other words little or no doping is required to form the body. This reduces the threshold voltage of the device, which (for an enhancement mode device) is the gate voltage below which no substantial current will flow in the channel. In such a device the body is floating, in other words its potential is independent of that of the substrate. A so-called “floating body effect” is caused by charges accumulating in the body of a PDSOI.
Control of the channel may also be enhanced by equipping the semiconductor device with more than one gate. Not only the body but also the BOX may be made very thin. If the BOX is sufficiently thin (so-called Ultra-Thin BOX or UTBOX of 25 nm or less), it is possible to influence the body via the underside of the structure, for example by implanting a back-plane under the BOX. Thus, in such a device a second gate may be formed at the underside or rear of the silicon layer. In such a structure, the top gate is referred to as a “front” gate and the underside or rear gate contact is referred to as a “back” gate. It should be noted that such a back gate need not have the same structure as the top gate. There need not be a well-defined gate stack in the same way as for the top gate, indeed the back gate may be more implicitly than explicitly formed.
It should also be noted that in such multi-gate devices, it is possible to consider more than one channel, each of which may be operating simultaneously in the device. Thus, in a UT device to be discussed it may sometimes be convenient to refer to both a “front” and a “rear” channel. Alternatively, these may be viewed as distinct regions of a single channel. Assuming that the back gate, for example, is held at a steady potential, it is still possible to refer to a single threshold voltage VT as the voltage level which, as the front gate voltage is “swept” upwards, turns on the front channel.
Devices with ultra-thin body and BOX will be referred to below as UT devices.
An alternative multi-gate structure is the so-called finFET and its variants. This structure may employ the ultra-thin body/BOX referred to above, but rather than provide a second gate on the back of the device, this structure provides the body as a fin of silicon perpendicular to the BOX, allowing multiple gates to be formed along the sides and/or top of the upright fin. By forming gate material at the sides of the fin but not at the top, the gates may be made electrically independent.
Multi-gate transistors including finFETs may also be bulk devices.
The gates of a multi-gate MOS device may have the same, or different, dimensions and properties. That is, different “strengths” of gate may be provided by varying the oxide thickness and/or the work function of the gate electrodes between the respective gates.
The application of voltages to the terminals of a semiconductor device is referred to as “bias” and multiple gate devices may be biased in various ways, including biasing both gates in common, or (if the gates are electrically separated) independently.
Different bias conditions will place the MOS device in one or other of the possible states or modes referred to as accumulation, depletion or inversion. The transitions between these modes are governed by two specific bias voltages (gate voltages, or more correctly voltage difference between gate and source/drain): the threshold voltage VT mentioned earlier, and a flatband voltage Vfb. These will now be outlined with reference to a bulk n-channel MOS (nMOS) by way of example.
Assume that the device first has a negative gate potential. Holes are attracted from the semiconductor body to the body/gate oxide interface, owing to negative charge on the gate; this is referred to as accumulation. As the gate voltage rises (becomes more positive) the flatband voltage is reached, and this marks the transition between accumulation and depletion. The term flatband implies that the energy band diagram of the device is flat, i.e. no net charge exists in the body. At this point, the applied gate voltage equals the difference in work function between the gate electrode and the semiconductor.
In the depletion mode (also called the subthreshold region of operation), the positive charge on the gate pushes the holes towards the substrate, leaving the body (at least in the region under the gate) depleted of charge carriers, and forming a depletion layer. The depth of this layer increases as the gate voltage rises. In this mode, the transistor is considered to be turned off; in reality, however, a small subthreshold current flows which is a function of the gate-source voltage.
As the gate voltage rises further beyond the threshold voltage, the depletion mode gives way to inversion, in which a negatively-charged inversion layer is formed at the gate/body interface in addition to the depletion layer. Thus, when the drain-source voltage VDS is sufficient, current flows between the drain and source. (Incidentally, in this specification, the terms drain-source, source-drain and drain voltage are synonymous unless otherwise demanded by the context; thus generally VD≡VDs. In addition, a “channel region” may be referred to for convenience even in the absence of the inversion mode
The transistor is now considered to be turned on. As the gate voltage increases, the current increases more or less linearly; thus the transistor acts as an amplifying element, which property is utilised in various analog circuits. Further increase of the applied bias voltages will cause the channel to grow in size, increasing the channel current up to a saturation level, so-called pinch-off.
The above explanation refers to bulk transistors, but the above modes likewise exist also for non-bulk devices. In UT devices the inversion layer can occupy the entire body.
A single channel was assumed for the purposes of the above explanation, but in a multi-gate device, it is possible for the channels (or viewed another way, different regions of a single channel) to be in different modes simultaneously. In fact, the present invention exploits this possibility as will be explained below.
As indicated above, highly-scaled transistors are difficult to turn off completely. As a measure of how easy or difficult it is to reduce the drain current, Subthreshold Slope (SS) is an important parameter. This represents the amount of change in gate-source voltage Vgs needed to produce a given change in drain current ID. More formally SS=d(Vgs)/d(log(ID)). The smaller the value of SS, the better as the more abrupt is the transition between subthreshold and inversion modes.
Conventional MOS devices cannot provide an SS below 60 mV/decade, and this is a limiting factor on reduction of operating voltage. UT devices including finFETs allow a lower (=better) SS to be obtained because of the improved gate control and absence of doping. Other novel forms of transistor have been proposed to overcome the above limitation on SS, such as the tunneling FET (TFET), Nano-Electro-Mechanical FET (NEMFET), Impact-ionization MOSFET (IMOS) and Feedback FET (FB-FET). Generally these are “asymmetric” devices; that is, properties such as source and drain characteristics, which are the same in conventional, symmetric MOS transistors, differ between the source and drain which necessitates additional processing.
Relying on band-to-band tunneling current, the TFET realizes <60 mV/dec SS at low gate bias. Since SS is a function of gate bias, it is difficult to keep <60 mV/dec SS with current higher than 10−10 A/μm. Low ON-state current is also another major issue with the TFET.
By utilizing the movement of a mechanical gate, the NEMFET achieves an abrupt SS. However, the mechanical movement limits the operation speed and reliability.
The IMOS achieves a SS of <5 mV/dec as well as high ON-state current via avalanche breakdown. One major drawback of the IMOS is the high operation voltage (even with the use of SiGe as the body material) which leads to severe reliability problems.
The FB-FET has been proposed to reduce the operation voltage. However, like TFET and IMOS, FB-FET is an asymmetrical device which is not compatible with standard CMOS and requires initial programming to set the device states. It also suffers from the reliability problem of charge injection into sidewalls during operation.
As already mentioned, MOS transistors may be employed in various ways in ICs including as switches in logic circuits and amplifiers in analog circuits. Additionally it is possible to use specific kinds of MOS transistor structure as a dynamic random access memory (DRAM) or static random access memory (SRAM).
That is, not only can a MOS transistor be combined with a charge-storing capacitor to form a conventional 1T1C (one transistor, one capacitor) DRAM cell, or combined with other transistors in a latch to form a SRAM cell, but under certain conditions an individual MOS transistor may exhibit an intrinsic memory characteristic and thus form a 1T memory cell, also called capacitorless DRAM. This intrinsic memory characteristic exploits the floating body effect referred to earlier.
Two such specific transistor structures are Z-RAM and the BJT-based floating body cell (FBC).
Z-RAM (Zero-Capacitor RAM) exploits the floating body effect by utilising the variable capacitance which exists between the transistor body and the substrate, this variable capacitance taking the place of the conventional capacitor of a 1T1C cell.
The BJT-based FBC, which offers high sense margin and longer static retention time, has received considerable attention. This device exploits the parasitic bipolar junction transistor (BJT) which, in the equivalent circuit for a MOSFET, exists in parallel with the MOSFET. Conventionally this parasitic BJT is a problem: if the BJT turns ON, it cannot be turned off since the gate has no control over it, so-called “latch-up”. The BJT can be turned on due to a voltage drop across the p-type body region, which is normally to be avoided at all costs.
In contrast, the basic idea of the BJT-based FBC is to write ‘1’ by latching the parasitic BJT. However, the high bias conditions which are required to achieve this degrade the reliability significantly. This is especially true for fully depleted devices where the BJT feedback loop can be much weaker as compared to partially depleted devices. Due to the latch occurrence condition, i.e. β(M−1)≧1, where β=parasitic BJT gain and M=impact ionization multiplication factor, the BJT based FBC requires a high operation voltage. A bias of up to 3.6V is needed to get the hysteresis window, and significant degradation is linked to this high VDS. Moreover, the need for relatively high bias voltages conflicts with the drive towards lower operating voltages of ICs.
Consequently, it would be highly desirable to provide a semiconductor device capable of acting as a 1T memory cell without requiring high bias voltages.
It would further be highly desirable to provide an integrated circuit with identically-fabricated semiconductor devices capable of use as either 1T memory cells, logic switches or analog elements, depending only on the biasing scheme used.